In previous blogs, I have explained how new non-volatile memory technologies will play an increasing role for embedded and computing applications. In one of my August Blogs I mentioned that it looked like Intel’s Optane memory might finally have reached enough production volume to make it profitable at the price it has to sell to be competitive with DRAM. The figure below of the Coughlin Associates and Objective Analysis Report on Emerging Memories Find Their Direction, shows our projections for the growth in shipped capacity for Magnetic Random Access Memory (MRAM) and 3D XPoint (Intel Optane memory) as well as more conventional NAND flash memory and DRAM.
There was evidence of the increasing use of MRAM, resistive RAM (RRAM), and 3D XPoint memory during presentations at a recent TSMC Online Technology Symposium as well as at the 2020 conference. IEEE Hot Chips. In addition, chip company AI Ambiq has announced MRAM in its latest generation Apollo System on Chip (SoC) family. Let’s look at some of these developments.
TSMC hosted an online tech symposium I attended where the company where Kevin Zhang talked about his latest developments including 7, 5 and even 3nm semiconductor technologies. In addition, the company’s annual report provides information on how the company will use emerging non-volatile memory technologies in on-board products.
The company’s annual report states that TSMC’s 22nm resistive RAM (RRAM) began production at risk in 2019 and is expected to complete IP reliability qualification in 2020. The 40nm RRAM has achieved technical qualification while consumer product qualifications continued. TSMC has stated that there will be multiple customer registrations during the second half of 2020. The company’s RRAM is intended for use in low-cost microcontroller microcontrollers and AI memory devices of the Internet of Things.
The 22nm on-board magnetic random access memory (MRAM) IPs are expected to complete their reliability qualification in 2020. In addition, the company’s 16nm MRAM is under development and progressing well. Risk generation for eFlash-type MRAM is expected in T421 and SRAM-type MRAM is expected in T422. The company sees MRAM replacing eFlash in high reliability microcontrollers, including for AI, IoT and automotive AEC-Q100 Grade-1 applications.
One of TSMC’s customers, Ambiq, is developing chips that will enable the next generation of battery-powered speech recognition IoT terminals. Company 4e The Apollo SoC family sets new standards for ultra-low power smart IoT devices. The Apollo 4 is implemented with TSMC’s 22nm ULL process and 32-bit Arm Cortex-M4 kernel with Floating Point Unit (FPU) and Arm Artisan physical IP.
The SoC chip achieves power consumption as low as 3 microA / MHz using MRAM with low deep sleep current modes and operates up to 192 MHz clock frequency with TurboSPOT (power optimized technology sub-threshold), SPOT) and with a 2D / 2.5 D graphics accelerator and MIPI DSI 1.2 with up to two lanes at 500 Mbps per lane.
The figure below shows the block diagram showing various features including 2MB MRAM with up to 1.8MB SRAM. BLE Radio blocks are in the Bluetooth version of the chip.
Ambiq claims that the Apollo4 has enough compute and storage resources to handle complex algorithms and neural networks while displaying vivid, crystal-clear and fluid graphics. If additional memory is required, external memory is supported through Ambiq’s multibit SPI and e.MMC interfaces.
According to Ambiq, the Apollo4 is uniquely designed to serve as both an application processor and co-processor for battery-powered terminals, including smartwatches, children’s watches, fitness bracelets, animal trackers. , far-field voice remotes, predictive health and maintenance devices. , smart security devices and smart home devices.
The product is intended for use in intelligent endpoint IoT devices with permanent voice processing.
At the IEEE Hot Chips 2020 conference, there were some interesting announcements related to emerging memories. Intel gave a talk on its Ice Lake server product where it stated that its Total Memory Encryption (TME) encrypts data in DRAM using AES-XTS-128 bit encryption. They also mentioned the use of Intel Optane Persistent 200 series (Barlow Pass) memory.
Intel also described latency and consistency optimizations that help the product and use memory more efficiently, including Optane. In particular, Intel said they can minimize the impact of persistent memory latencies on performance. Intel also included non-volatile memory as a processor differentiator during a Tiger Lake presentation. Also mentioned was the need for new high capacity, low power, low latency memory tightly coupled with compute as discussed below.
IBM spoke about its latest POWER10 processor for supercomputing applications (built with Samsung’s 7nm foundry), which included support for non-volatile storage class (SCM) memory, similar to persistent memory (PM). ) from Intel. As shown in the figure below, the Open Memory Interface (OMI) provides high capacity, encrypted persistent memory in a DIMM slot (possibly Optane DIMMs). IBM states that POWER10 can support 2PB of addressable load / store memory.
IBM is also seeing a high-capacity encrypted persistent SCM attached to FPGAs or ASIC accelerators for a POWER10 host with high bandwidth and low latency using an open coherent accelerator processor interface (OpenCAPI). . POWER10 can also allow one system to map the memory of another system like its own. Multiple systems can be grouped together, sharing each other’s memory on a petabyte scale.
Emerging memory for compute, IoT and AI / ML applications was showcased at a recent TSMC technical conference, at the Apollo4 SoC announcement by Ambiq, and in discussions by IBM and Intel at the 2020 IEEE conference Hot Chips.